A Novel Multi Membership Function Based VLSI Architecture of a Fuzzy Inference Processor

In this paper, we propose, simulated and modelled, first time, a novel fuzzy inference processor capable of handling three types of membership functions together. To implement the proposed inference processor, a novel multi membership function (MMF) MAX-MIN calculator circuit, calculating the matching degree (MD) between three types of membership functions (MF): Gaussian, Trapezoid and Triangular together has been designed and implemented. On the basis of the proposed MAX-MIN calculator, other blocks of the fuzzy inference processor, such as, fuzzy decoder, fuzzy inferencing system and defuzzifier have been designed. The novelty of the fuzzy processor and its constituents lies in handling the MMFs in comparison to the exiting architectures which deal with just one MF. The proposed architectures are area, power and speed efficient in comparison to the existing architectures, as can be seen from the implementation reports. The field programmable gate array (FPGA) implementations of proposed MMF based MAX-MIN calculator and MMF based fuzzy inference processor have revealed that significant reductions in FPGA resource consumption in the proposed architectures have been achieved in comparison to the combined resources of the architectures based on Triangular, Trapezoid and Gaussian MFs used earlier.